Semiconductor random access memories (RAM) are typically formed of row lines and columns crossing the row lines. Memory cells, that store charge, are located adjacent each crossing of the rows and columns. Thus, accessing any bit in the RAM given its row and column address is analogous to locating the bit in an array given its (x, y) coordinates. Each bit of information stored in a memory is a tiny capacitor that stores the value of the bit as a `high` (VCC) or `low` (GND) voltage. The rows and columns are selected by respective row (or x) decoders and column (or y) decoders which receive memory addresses so as to read and write to particular bit cells.
Typically data is accessed in bits or words, thus groups of memory cells in a given word are generally connected to a common wordline which may then be activated by a decoded, address signal applied thereto. The individual bits across each word are connected to common bitlines. For example, in a dynamic random access memory DRAM a single column or complimentary bitline pair is typically coupled to a differential sense amplifier, a column select, precharge circuitry and a collection of storage cells. The storage or bit cells may have a single port for reading and writing.
In a typical DRAM there are actually several bitlines each tied to respective sense amplifiers. In a read operation, every bit in a selected row or wordline is sensed by its respective sense amplifier. The selected column is then read out onto a local data bus. A write operation is similar, the value to be written is first fed into each sense amplifier over the local data bus. The sense amplifier then writes this value into the selected column's storage cell. Furthermore, once capacitors are used as storage cells in a DRAM, the charge stored in each cell tends to leak away over time. Therefore, it is necessary to refresh the value in each cell periodically. In typical DRAMs each row must be refreshed every 16, 30, 64 or 128 msec. Refreshing a row is similar to reading it except the data does not emerge from the columns. In a refresh operation each bit in a selected row is moved to its respective sense amplifier. Each sense amplifier then amplifies the value on its bitlines and drives the refresh value back into the storage cell.
There are sometimes physical faults caused by manufacturing defects associated with the cells in a particular column or row. For this reason, RAMs usually contain redundant (spare) columns and rows. These redundant memory cells are used in the memory array in order to effect replacement of defective memory cells, word lines and bitlines. In a typical DRAM process both word lines and bitlines must be replaced in order to achieve economic yields. For embedded DRAM macro cells in order to increase the data bandwidth of DRAMs and application specific integrated circuit (ASICS) it is necessary to dramatically increase the word width.
Recent integration trends have resulted in embedding DRAM in ASIC processes. One main advantage of embedded DRAM implementation is a substantial bandwidth increase, since the data to and from the memory does not have to be transferred externally.
A problem with wide word widths however, is the difficulty in handling bitline redundancy. Implementing bitline redundancy by replacing a column address results in a large substrate area overhead due to a large number of cells reserved for redundancy. Typically, the ratio of redundant bitlines to normal bitlines is about 3%. However, as the occurrence of defective memory is unavoidable, chip manufacturers have devised various schemes to allow replacement of this faulty memory at manufacture time.
In one implementation, for example, in an embedded wide word DRAM macro cell replacement of memory blocks with redundant memory blocks is handled by additional logic circuits on the data 1/0-lines, this method is inefficient in that it occupies a large area and consumes a large amount of power.
Other schemes provide redundant y decoders for the addressing of the redundant columns in order to allow the disabling and replacement of the faulty columns. Circuitry for addressing the redundant columns is relatively simple compared to the problem associated with re-routing the redundant data path to the data 1/0 of the memory.
In U.S. Pat. No. 4,691,300 an apparatus and method for redundant column substitution in a memory device with column redundancy is described. Rather than inhibiting normal column decoding and selecting a redundant column in a response to a defective column address, this patent describes a method that proceeds in parallel with normal column access and redundant column access. An 1/0 multiplexer is provided which receives both the normal and redundant data and in response to an input from the redundant column decoder selects the redundant data. Furthermore, the redundant columns have to be located physically close to the 1/0 multiplexer. This invention requires the provision of additional redundant column select and redundant column decoder circuitry.
In U.S. Pat. No. 5,673,227, utilizes a redundant multiplexer which is programmed by a fuse circuit for determining which of the top or bottom redundant data lines replaces a defective column data line. This invention requires additional circuitry for fuse decoders and the redundant multiplexers.
In U.S. Pat. No. 4,281,398, block redundancy is utilized to replace defective memory blocks. Block redundancy selection is implemented through a multiplexer and repair buffer which are coupled to the data node input/output circuitry. The redundant block substitution is carried out by selectively applying a high voltage on the output data terminal of the block in which the bad bit is located. A separate programming current supply is provided for blowing a polysilicon fuse in the repair buffer which electrically disconnects the bad block of memory while simultaneously substituting a redundant block in its place.
In U.S. Pat. No. 5,359,561, a memory device is described which includes a plurality of data lines at least one redundant data line and one common data line. Column switches for reading and writing are installed between the data lines of the non-normal columns and a common data line and between the data lines of the redundant column and the common data line. A column decoder is provided for controlling the plurality of column switches to select the appropriate normal or redundant columns for read and write operations.
In U.S. Pat. No. 5,600,277, DRAM redundancy fuse circuit is described and used CMOS pass gates to choose one of a pair consisting of a binary logic signal and its compliment logic signal. The circuit utilizes NMOS transistors as pass gate devices the gate terminals of which are driven by boosted Vpp supply.
The disadvantage of the circuit is the control circuit for the pass gate switches occupy a greater area on the chip in comparison to other CMOS passgate circuits. Furthermore, the greater number of components used in this design increases the current continuation and the probability of the circuit failure, particularly if the circuit is duplicated a number of times in a given semiconductor memory such as for a redundancy selection circuit in wide data bus memories.
In U.S. Pat. No. 4,389,715 this patent describes a redundancy circuit in which defective row addresses and defective column addresses are stored. A comparator sequentially compares the defective memory cell addresses against incoming address data. When the comparator senses a match, a control signal is generated to initiate substitution of spare memory cells for the defective memory cells.
Accordingly, there is a need for an improved redundancy fuse pass gate circuit which makes minimal use of semiconductor area, has a decreased current consumption and setting time, and minimizes the number of devices constituting the circuit, thereby improving reliability of the circuit.